[16 April 2012] A Laser Communication System for Voice Transmission

16 April 2012

National University of Singapore

EE1003 INTRODUCTION TO SIGNALS AND COMMUNICATIONS
A Laser Communication System for Voice Transmission

Project Report

Abstract

The aim of this project is to transmit analog sound from a commercial mp3 player digitally using a store-bought laser pointer as the transmitter. This will be achieved mainly by performing analog-digital conversions, and by using a digitally phase-locked loop (DPLL) to synchronize the clock signals on both the transmitter and the receiver. This project was carried out in Jan 2012 - April 2012 as a group of 5 team-mates.

Contents

1      Scope

• 1.1  Background 
• 1.2 Problem Identification  
• 1.3 System Overview 
• 1.4 Project Sub-Group Divisions
• 1.5 Constraints

2      System Design and Implementation

• 2.1 Obtaining the Clocking Signals on the Transmitter Unit
• 2.2  Transmitter Unit’s PCM Decoder Circuit
• 2.3  Transmitter Unit’s Training Sequence Generation Circuit
• 2.4  Receiver Unit’s Training Sequence Detection Circuit
• 2.5  Recovering the FSYN Signal at the Receiver Unit
• 2.6  Recovering the MCLK and BCLK Signals at the Receiver Unit
• 2.7  Receiver Unit’s Photodiode Detector Circuit
• 2.8  Receiver Unit’s PCM Decoder Circuit

3      Special Features 

• 3.1  Bluetooth Microphone Transmission
• 3.2  Speaker Volume Control
• 3.3  Improving the Efficiency of achieving laser-photodiode Link-Up
• 3.4  Auto-Feedback Emergency System.

4      Summary

• 4.1  Overall System Performance
• 4.2  Reflections

5      References

• References

1 Scope

1.1 Background

Since the beginning of civilization, man has sought to communicate with each other over long distances. From the primitive usage of smoke signals to groundbreaking technologies of their time such as the telegraph and telephone, communication technology has seen rapid improvement and development in recent years into today’s 3G/4G cellular data networks and fiber-optic internet linkage which are commonly used by people worldwide. The ability to convert analog signals to digital ones for transmission has revolutionized the communication industry.

Out of the various types of analog-digital transmissions, the Pulse Code Modulation (PCM) scheme is one of the most common. Apart from its usage in audio recording and compression, the PCM scheme is also used in Public Switch-Telephone Networks (PSTNs), whose primary objective is to use a modulation scheme to convert analog human voice signals into digital signals for transmission, and also to be able to convert the digital signals back into the original analog signal after reception.

In comparison with analog transmissions, digital data transmissions have the significant advantage that discrete and finite levels of digital signals have intervals which cause it to be less vulnerable to distortions caused by ambient noise, which in turn make recovering the signal much easier. One way of transmitting digital data wirelessly is by using a laser beam. As digital signals are purely made up of ones and zeroes, we can take the laser beam being ‘on’ as sending a ‘1’, and take the laser beam being ‘off’ as sending a ‘0’.

Also, using laser communication systems increases cost effectiveness when compared to the conventional method of copper wire. A basic laser communication system can transmit data a few hundred meters. Throw in a parabolic light reflector and it may achieve a transmission distance of a few kilometers. Furthermore, the laser link is highly secure as it is virtually impossible for an external party to tap into the link, as any interception will cause a break in data flow, alerting the user immediately. From this discussion, the benefits of a laser communication system can be clearly seen.

1.2 Problem Identification

Figure 1. Basic PCM Encoder/Decoder Chip Schematic

Before beginning the project, our group first considered the basic building blocks of an analog-digital data transmitter. We had all performed this task before in our weekly 3 hour pair-work lab sessions earlier this semester before we started on this project. Figure 1 shows a simple example of how 2 PCM encoder/decoder chips are connected to take in and output an analog signal while transmitting it digitally. Circled in Green is the connection through which the actual data is being transmitted. Circled in Red are the 3 clocking signals, generated externally, essential for both chips to work in tandem. The 3 clocking signals are namely the Master Clock (MCLK), Bit Clock (BCLK) and the Frame Synchronization (FSYN).

One might then question why it takes a group of five people two months to achieve something which we have already achieved in pairs and took us no more than 3 hours. The reason is simple, for us to convert the schematic in Figure 1 into a wireless communication system, we have to remove any and all wired connections between both chips. For visualization purposes, imagine Figure 1 being cut in half vertically down its center. It is not just a matter of replacing the data connection (circled in green) with a laser transmitter/receiver circuit. More importantly, we have to retrieve 3 clock signals (circled in red). The signals not only have to be at the same frequency, they also need to have their edges have aligned within a few nanoseconds of each other. This brings about some problems which were essential for us to consider before we began the planning and design phase of our project.

1.3 System Overview

After considering the problems identified and revising what we had learnt in the first half of the semester, we came up with the following Block Diagram for our project:

Figure 2. Project Block Diagram

For the transmitter unit, we would need to build the following circuits:

• A PCM Encoder Circuit which would convert the raw audio signal we fed into it from analog to digital format. The digital output would then be fed directly into a laser transmitter.
• A Clock Network Circuit to divide the frequency, and adjust the duty cycle, of the square wave generated by the signal generator to the required values of our MCLK, BCLK and FSYN signals.
• A Training Sequence Generation Circuit to help synchronize the FSYN signal on the transmitter unit with that of the receiver unit.

For the receiver unit, we would need to build the following circuits:

•  A Photodiode Receiver Circuit to detect and amplify the signal received from the laser transmitter.
• A PCM Decoder Circuit which would convert the digital signal received from the laser transmitter back into an analog one for output.
• A Digital Phase-Lock Loop (DPLL) Circuit which would help align the edges of the receiver unit’s MCLK and BCLK signals with those of the transmitter unit’s.
•  A Clock Network Circuit to divide the frequency of the square wave generated by the signal generator to the required values of our MCLK and BCLK signals.
• A Training Sequence Detection Circuit to help synchronize the FSYN signal on the transmitter unit with that of the receiver unit.

1.4 Project Sub-Group Division

After coming up with our block diagram and deciding what circuits we needed to build, our group decided to divide the project firstly into the Transmitter and Receiver portions, before breaking down the project into 5 subgroups which each individual member would be in charge of. The subgroups are:

1. Transmitter, PCM Encoder Circuit and Clock Network Circuit
2. Transmitter, Training Sequence Generation Circuit
3. Receiver, Training Sequence Detection Circuit and Frame Synchronization Circuit
4. Receiver, DPLL Circuit and Clock Network Circuit
5. Receiver, PCM Decoder Circuit and Photodiode Receiver Circuit 

1.5 Constraints

• Time and manpower shortage was a huge constraint for this project. Though we were given 6 weeks to design, implement and debug this project, we were only allocated a single 3-hour lab session every week. Thus, the five of us virtually had less than a day to complete this project from scratch.
• Shortage of components was another constraint. Although we were given spare parts, they were given to us proportionally based on what we were expected to use, and not based on their likelihood of breaking down. This resulted in us having to make multiple trips to electronic stores to purchase additional components.

2 System Design and Implementation

2.1 Obtaining the Clocking Signals on the Transmitter Unit

As stated earlier, both the transmitter and receiver units require virtually identical MCLK, BCLK and FSYN signals in order for the system to work. The analog signal we were transmitting was music from our mp3 players, and the bandwidth of the human voice lies roughly between 0.2 kHz and 4 kHz. To avoid aliasing during sampling, we used the Nyquist rate concept which states that sampling frequency should be greater than or equal to double the frequency of the sampled signal. Thus we chose to use an 8 kHz, 12.5% Duty Cycle FSYN Signal, which meant that 8000 frames of information would be transmitted every second. Since there were 8 bits of data in each frame of information, we then needed a 64 kHz TTL (50% Duty Cycle) BCLK Signal. We also decided to use a 2.048 MHz TTL MCLK signal.

After deciding the values for our clocking signals, we decided to output the 2.048MHz TTL MCLK Signal using the signal generator directly, and then divided the frequency of the MCLK signal by 32 and 256 to obtain the 64 kHz BCLK Signal, and an 8 kHz TTL signal respectively. We then adjusted the duty cycle of the 8 kHz TTL signal to 12.5% to obtain the FSYN signal.

Figure 3. Clock Network Circuit Schematic for Transmitter Unit

As shown by our schematic in Figure 3, our frequency divider circuit consisted of two 4-bit synchronous counter chips (74HC191), being used as divide-by-16/8 frequency dividers and one D flip-flop (74HC74) used as a divide-by-2 frequency divider. By cascading one of the 74HC191 chips with the 74HC74 chip, we obtain a total dividing factor of 32, which provided us with the 64 kHz BCLK. By cascading all three chips together we obtained a total dividing factor of 256, which provided us with the 8 kHz frame synchronization clock. Also, the MCLK was generated by the oscilloscope as a TTL signal, thus its duty cycle was already at 50%. By connecting the pins as shown in Figure 3, we were able to obtain a 50% and 12.5% duty cycle for the BCLK and FSYN signals respectively.

2.2 Transmitter Unit’s PCM Encoder Circuit

Figure 4. PCM Encoder Schematic

As shown in Figure 4, we used a TP3054 chip for PCM modulation. As stated in section 2.1, the range of the human voice lies roughly between 0.2 kHz and 4 kHz. Thus a low pass filter of bandwidth 4 kHz is utilized to reduce distortion from ambient noise. Any input analog signal will have to pass through the low pass filter before being modulated. The Data is output to a Multiplexer (MUX) Unit which will be elaborated upon in the next section.

2.3 Transmitter Unit’s Training Sequence Generation Circuit

A training sequence is a unique series of 8 binary digits chosen by our group. This training sequence is supposed to have no pattern (e.g. 11111111, 11001100 or 10101010). This is so as the more unique the training sequence, the lesser the chance that the receiver will falsely identify training sequences. For this project, our group chose “10100101” as the training sequence.

In order to achieve frame synchronization with the receiver unit, we decided to implement a ‘serial schematic’ for our system. This means that we repeatedly sent training sequences until the frame synchronized clock in the receiver side was set-up successively before manually switching to transmission of real data. This may sound time consuming, but since 8 thousand Training Sequences can be sent every second, we were able to achieve frame synchronization in a matter of seconds. The schematic for this circuit is as shown in Figure 5.

Figure 5. Training Sequence Generation Circuit

The 74HC165 chip is a ‘parallel-in, serial-out’ shift register. It will read the parallel VCC/GND singular input ‘bits’ (D7 down to D0) and output them serially as a string of 8 bits. According to its function table from the datasheet (shown in Figure 6), we had to connect the RCO signal from the divide-by-8 counter to pin “bar_PL” because it is active-low triggered. By using the RCO signal which was always high except for the last half a cycle at state 15, we were able to load a single 8-bit training sequence into the shift register once every frame cycle. Also, D0 to D7 corresponds to Q0 to Q7 respectively based on the register, and the chip is enabled by connecting pin CE to GND. The chip shifts and outputs one bit to Pin Q7 on every rising edge of the clock signal input at pin CP. In other words, the serial output corresponded to the values of D7, D6, D5, etc. all the way to the last “1” (D0), which corresponds to the ‘a-b-c’ segment in Figure 7. From ‘a-b’, ‘1’ is output normally. However, from ‘b-c’, RCO is low meaning a new training sequence is being loaded into the register. In this case, Q7 will still output high voltage because Q0 is high (refer to Figure 7). Thus, we had to ensure that the first and last digits of our training sequence were equal so that after every ‘a-b-c’ segment, the next training sequence will output serially as per normal.

Figure 6. Function Table for 74HC165 Chip

Figure 7. Illustrated CLK, RCO and OUTPUT for training sequence “10100101”

Since we were not provided with multiplexer chips, we built one ourselves by using three 2-input NAND gates as shown in Figure 8. By use of a manual switch, we were able to easily switch the output between real data and training sequences. Whenever we put the switch to Vcc, control outputs ‘1’ to branch 1, and the inverse (‘0’) to branch 2. In this case, training sequence will be the selected output_to_laser since branch 2 will always output 1 after the NAND gate. Whenever we put the switch to GND, then branch 1 will be ‘0’ resulting in the real data being fed into the laser beam for output.

Figure 8. Multiplexer Combinational Logic Circuit Design

However, taking into consideration the ‘bouncing’ problem caused by the mechanical switch, we needed to include one D-flip-flop (74HC74 chip). Since there is no need for us to reset and set the current Q value, we disabled pin RD and pin SD by connecting them to VCC. The D-flip-flop is a basic sequential logic which has a memory of one bit per clock cycle. Therefore, it helped us to avoid bouncing problems as well as to locate the exact switching position between training sequence and real data frames.

As illustrated in Figure 9, the D-flip-flop will change its value only during the rising edges of the frame clock. Thus, the last training frame sent after switching to transmission of real data had its last bit replaced by the last bit of the real data frame. However, this does not influence the generation of the synchronized frame clock at the receiver because at the receiver unit, the counter was disabled automatically after counting 16 training sequences while at the transmitter unit, it sent far more than 16 training sequences. Thus, this did not have any impact on the generation of the FSYN signal.

Figure 9. Timing for Signal Transmission in ‘switching’ state (Transmitter)

2.4 Receiver Unit’s Training Sequence Detection Circuit

Figure 10. Timing for Signal Transmission in ‘switching’ state (Transmitter and Receiver)

As can be seen from Figure 10, the FSYN is leading the training sequence by one BCLK period. When the shift register detects the training sequence, it will output “TRUE” during that BCLK period, which is also the clock for the mod-16 counter. As a result, the detection circuit output will be synchronized with the FSX from the transmitter unit. Consequentially, the MAX/MIN output from divide-by-16 counter will be synchronous with FSX.

The MAX/MIN output will also trigger the LOAD input for the divide-by-8 counter. Thus, the MAX/MIN output from the divide-by-8 counter will be one BCLK period ahead of the transmitter unit’s FSX. As a result, the data needed to be delayed accordingly.

This was achieved by using a D flip-flop. As the DPLL circuit (refer to section 2.6) had already synchronized the receiver unit’s BCLK signal with that of the transmitter unit’s, we just used a D flip-flop to delay the FSYN signal by exactly one BCLK period (Figure 11).

Figure 11. D Flip-Flop configured to delay FSYN signal by one BCLK period

We then used an 8-bit serial-in, parallel-out shift register chip (74HVC164), shown in Figure 12), to detect the training sequence. The output at pin Q0 is the product of the Boolean ‘AND’ operation of inputs at pin A and pin B. Hence, by connecting pin A to data and pin B to VCC the output at Q0 will be equal to the data. The recovered BCLK is used to detect the training sequence and is connected to pin CP which is triggered by rising (low to high) edges of the BCLK. To avoid a low-level input on the master reset which overrides all other inputs, we connect ‘MR_Bar’ to Vcc. As for the combinational logic circuit (shown in Figure 12) to detect the “10100101” training sequence all pins with output ‘1’ are passed into NAND gates which will then output ‘0’ only when all inputs are ‘1’. All pins with output ‘0’, are passed into OR gates which will then output ‘0’ only when all the inputs are ‘0’. Finally, we OR the outputs together and then invert that output. Therefore, the final output will be ‘1’ only whenever a correct training sequence is detected.

Figure 12. Training Sequence Detection Combinational Logic Circuit

2.5 Recovering the FSYN Signal at the Receiver Unit

Technically, we could have switched to real-data transmission once we have received a single training sequence. However, it is very possible that a particular 8-bit segment of the data will be identical to the training sequence. To avoid this, we added a ‘mod-16’ counter to detect the training sequence 16 consecutive times before it begins generating the FSYN signal. In comparison, the chance of a stream of data being identical to the training sequence 16 times in a row is virtually zero.

Once the counter counts up to 15, the MAX/MIN output becomes high for one BCLK period, and RCO(bar) output becomes low. The MAX/MIN output is used to trigger the divide-by-8 counter to get the FSYN signal from the BCLK signal recovered by the receiver unit’s DPLL Circuit (Section 2.6).

However, we also needed to simultaneously disable the ‘mod-16’ counter used to count the number of training sequences detected. This is because when we switch to data, we no longer want the system to detect training sequences, if not the MAX/MIN output will go back to zero and we will not be able to obtain the FSYN signal anymore. We disabled the count-16 counter by feeding RCO(bar) and the detection output into a NAND gate then inverting the output. Once the counter counts 16 times, RCO(bar) becomes low and the clock will be low. Following which, RCO(bar) will remain low, disabling the counter until we manually reload it again.

As shown in Figure 13, we fed the recovered BCLK Signal into the CLK input of a 74HC191 counter chip, set inputs DCBA to “1000” and connect QD to load. Subsequently, we performed a Boolean NAND operation with the outputs from QD and MAX/MIN. Once the ‘mod-16’ counter is disabled, MAX/MIN will remain high and the load depends solely on QD. We can finally recover the FSYN signal.

Figure 13. FSYN Signal Recovery Schematic

2.6 Recovering the MCLK and BCLK Signals at the Receiver Unit

In order to recover the MCLK and BCLK signals, we made use of a Digital Phase-Lock Loop (DPLL) Chip. We can input a high-speed clock along with the data received from the laser transmitter into the DPLL chip, and it will lock both signals in phase. We could then make small adjustments to the frequency of the high-speed clock to align the edges of the BCLK signals from the transmitter and receiver unit. Due to the error induced by adjusting the frequency of the high-speed clock, we have decided to use a 32.768MHz TTL signal. Thus, when we divide the output by 512 to obtain the BCLK, the error induced by adjusting the frequency of the High-Speed Clock will also be made 512 times smaller and become negligible.

As shown in Figure 14, the signal from the laser transmitter will be fed into the DPLL chip (74HC297) at pin A2_PD and the 32.768 MHz high-speed clock TTL signal will be fed into pin K_CP and I/D_CP. K_CP is a divide-by-K counter and I/D_CP feeds the signal to I/D circuit where its frequency is divided by 2. After passing through the I/D circuit, the signal goes through two cascaded 4-bit synchronous counter chips (74HC191). By taking the output of QC from the first counter chip, we obtained a total dividing factor of 16 with respect to the high-speed clock frequency of 32.768 MHz and hence, we recovered the 2.048 MHz MCLK signal. We then fed the output of QD from the first counter chip into the CLK output of the second counter chip. We were then able to achieve a total dividing factor of 512 from the QD output of the second counter chip with respect to the high-speed clock frequency of 32.768 MHz and hence, recover the 64 kHz BCLK signal. Since the 32.768 MHz signal has been phase-locked with the incoming data, the recovered MCLK and BCLK signals will have their rising edges aligned with those on the transmitter unit.

Figure 14. DPLL and Receiver Unit’s Clock Network Schematic

One important factor to note is that as the K value of the divide-by-K counter increases, it will be more effective in mitigating jitter. However, it also makes it increasingly difficult to achieve phase lock. After much trial and error, we decided to set the inputs ABCD to “HHHH” which toggles K to the maximum value of 2¹⁷ = 131072.

After setting up the DPLL circuit as shown in Figure 14, we used training sequences from the transmitter unit to test the locking capability of the DPLL Chip. We displayed the BCLK signals from both sides on an oscilloscope, and by adjusted the frequency of our high speed clock to ensure that the phase difference between both signals is zero.

At first, our BCLK signals were unable to achieve phase-lock even after we adjusted the high-speed clock signal over a wide range. After debugging the 74HC191 counter chips, we isolated the problem to 74HC297 DPLL chip. After replacing it with a new chip, we were able to achieve phase-lock as shown in Figure 15.

Figure 15. Phase-Locked BCLK signals from both Transmitter and Receiver Units

Following which, we managed to obtain FSYN signals which were in-phase again. However, another problem occurred when we manually switched the transmission from training sequences to real data. DPLL lost its locking status and vibrated every now and then. In order to solve this big jitter problem, we changed our K value to 2¹⁷. After doing so, our phase-locked state remained stable even while changing between transmission of training sequences and real data. This result indicated that although increasing the K value may cost us more time to achieve phase-lock it also enabled us to obtain a more stable outcome. We also came up with another supplementary solution to this problem. To reduce the duration of time delay in switching, we added in toggle switches which acted as multiplexers with manual controls.

After the DPLL was working to expectation, we found that the frame synchronization was only achieved to a certain limit. When we powered off our circuit and powered it on again, the frame synchronization could not be achieved. At first, we assumed that there was some mistake within our combinational logic circuits. However, this was just a simple issue of neglecting to re-load the counter. Therefore, all we had to do was re-load the counter after powering off and on our circuit and we managed to synchronize the frame markers once again (Figure 16).

Figure 16. Synchronized FSYN signals from the Transmitter and Receiver Units

2.7 Receiver Unit’s Photodiode Detector Circuit

A laser pointer is connected at the transmitter unit which generates a laser beam with varying intensity, flashing at a rate faster than can be seen by the human eye. The change in the laser intensity is captured by a photodiode and fed into the Photodiode Detector Circuit. Figure 17 shows the signal transmitted by the laser beam, and Figure 18 shows the signal received by the Photodiode Detector Circuit.

Figure 17. Training Sequence (above) and BCLK (below) from the Transmitter Unit

 

Figure 18. Oscilloscope display of Training Sequence received by Photodiode Detector Circuit

As shown by the schematic in Figure 19, the photodiode converts the signal received into a current wave and feeds it into the current amplifier chip AD8011. The current increases proportionately with light intensity. This change in the current is amplified by the chip to a significant level and then converted into a digital signal which is then fed into the PCM Decoder Chip (section 2.8) which converts it back into an analog signal. Moreover, a simple filter around the photodiode detector circuits which contain a 0.01μF capacitor and a 10nF capacitor help to filter out excess noise.

Figure 19. Schematic for Photodiode Detector Circuit

2.8 Receiver Unit’s PCM Decoder Circuit

The PCM decoder on the receiver unit performs the reverse operation of the PCM encoder on the transmitter unit so as to retrieve the original information. It receives binary bits from the transmitter and stores it in the ‘received’ register. The digital to analog converter then reconstructs the analog signal and triggers it using the FSYN signal. Then the noise in this analog signal is filtered through a low pass filter and the analog signal becomes a reconstructed voice signal which finally is output through a speaker.

As shown in Figure 20, the recovered MCLK, BCLK and FSYN signals are fed into the PCM decoder chip (TP3057) along with the data received from the photodiode receiver circuit. The analog output is then fed into the speaker.

Figure 20. Schematic of PCM Decoder Circuit

3 Special Features

3.1 Bluetooth Microphone Transmitter

Instead of just transmitting an analog signal from our mp3 players, our group has also added in the option of using a microphone to transmit voice signals. This allows users to send real-time data rather than just recorded data. Also, as an added benefit, by linking the microphone to the transmitter via Bluetooth, users will be able to distance themselves from the transmitter circuit. This is useful in tactical scenarios as a laser travels in a straight line and the position of the user will be a give-away if the laser light is detected.

3.2 Volume Control for the Speaker

We have decided to feed the output from the PCM decoder into a LM386 amplifier chip which has a variable resistor connected to it in order to improve sound quality and more importantly, to give us some measure of volume control. The schematic is shown in Figure 21.

Figure 21. Schematic of LM386 Amplifier cum Volume Control Circuit

3.3 Improving the Efficiency of achieving laser-photodiode Link-Up

Through trial and error, we found it extremely difficult to aim the laser at the photodiode if we were to simply place the photodiode on a tripod stand. Thus, we came up with the solution of placing our photodiode against a white background. This enabled us to see exactly how far our laser had ‘missed’ the target and thus, we were able to aim our laser more efficiently.

3.4 Auto-Feedback Emergency System

During transmission, any interception of the laser link will cause a break in data flow from transmitter to receiver, requiring the user to be immediately alerted. We want to alert the user at the transmitter unit by automatically playing an audio clip at the transmitter unit should this occur. This can be implemented by using another laser link passing this information back to the transmitter unit from the receiver unit. The schematics for the circuits are shown in Figure 22 and Figure 23.

The idea behind our design is as follows; when the data is lost, the data detected by the receiver unit will be a constant stream of ‘0’s. Thus, we want to count this data 4096 times to ensure a string of 4096 ‘0s’ which will mean that the data is really lost. Therefore, we will pass the data received through an inverter and connect it to the LOAD pin of the first 74191 counter. The MAX/MIN output of the first counter serves as the CLK input of the second counter and the MAX/MIN output of the second counter serves as the CLK input of the third counter. This way, the MAX/MIN output of the third counter will be asserted once the count hits 4096.

We then connected MAX/MIN output of the third counter to the CLK input of a D flip-flop and the data input of the D flip-flop is connected to Vcc. We also connect the data fed through an inverter to RD(bar) of the D flip-flop. In this way, if data is ‘0’, the D flip-flop will output 1. Should the photodiode detector circuit detect a ‘1’, the D flip-flop will be reset and it will output ‘0’ unless the third counter counts ‘0’ 4096 times and gives a rising pulse to the CLK input of the D flip-flop.

Should the laser be blocked, we want the transmitter unit to switch back to sending training sequences instead of real data so that the receiver side can re-synchronize the BCLK and FSYN signals. However, there is problem that if the receiver can detect the training sequence but does not receive 16 training sequences in a row, the synchronization between both FSYN signals cannot be achieved. We solve this problem by performing a Boolean ‘OR’ operation with the RCO output from the mod-16 counter counting the number of consecutive training sequences received and the output of the abovementioned D flip-flop. Thus, if the FSYN has not yet been achieved, the RCO of the counter will remain high, so that the transmitter unit will keep sending training sequences. Once FSYN has been achieved and the laser is not blocked, both the RCO and D flip-flop outputs will be low. After which, the transmitter can begin to send data.

Should data be lost, we need to reload the mod-16 counter which counts 16 consecutive training sequences. We achieve this by performing a Boolean NAND operation with the data after the inverter and the MAX/MIN output of the third counter and connect this to the LOAD of the mod-16 counter. At first, when data is lost, the data after inverter is ‘1’, the MAX/MIN output is ‘0’ and LOAD output will be ‘1’. When the third counter counts to 4096, both the data after inverter and the MAX/MIN output will be ‘1’, and the LOAD output will then be ‘0’. Afterwards, the MAX/MIN output will be ‘0’ again, or if the data stream is not blocked, LOAD will be ‘1’ again, which achieves our purpose of reloading the counter for a short duration.

Figure 22. Feedback Schematic for the Receiver Unit

For the transmitter unit, as mentioned before, when the feedback laser sends ‘1’, the transmitter unit will send training sequences instead of real data. Also, when the feedback laser sends ‘0’, the transmitter unit will send real data. Therefore, we directly connect the feedback laser to the D flip-flop which chooses between the transmission of training sequences and real data.

Because we want to play an audio clip at the transmitter side when data is lost, we have another PCM codec at the transmitter side to play the music. We perform a Boolean AND operation with the DX output from the PCM decoder and the output detected from the feedback laser and connect them to the DR pin of the PCM encoder. Only when the laser feedback from the receiver is ‘1’ will the speaker play the music, otherwise DR remains at ‘0’.

Figure 23. Feedback Schematic for the Transmitter Unit

4 Summary

4.1 Overall System Performance

On the day of our group’s project demonstration, during our preparation, we were unable to achieve a stable phase-lock between the BCLK signals from both transmitter and receiver units. Whenever we switched between training sequence and data transmission, the signals would start to lose their ‘locked’ status. We performed a quick on-the-spot rectification and found that the ABCD pins on our DPLL Chip (74HC297) were not configured as we had planned. This caused the ‘K’ value of the chip to deviate from our tried and tested value of 2¹⁷. After this was rectified, we managed to achieve phase-lock and our system worked as desired.

During the actual demonstration, we were able to successfully achieve the project’s basic requirements. All of the circuits mentioned in section 2 which we built functioned well as an integrated system, and we managed to successfully transmit an audio clip from an iPhone over a distance of approximately 5 meters using a laser beam as our medium of transmission. Also, we were very satisfied with the sound quality of the audio clip played by the speaker on the receiver unit. We could hear the music loud and clear, and there was almost no background noise at all. Also, most of the special features we implemented served us well and either provided our system with additional functions, or improved its efficiency.

One minor setback we faced was that we were unable to realize the special feature of the emergency auto-feedback (section 3.4). Our system was not able to automatically re-synchronize the clocking signals whenever the laser link was intercepted. As a result, we had to manually re-synchronize our clocking signals using toggle switches whenever the laser link was severed.

4.2 Reflections

Through this project, we had not only learnt the basic theory behind PCM voice transmission, we had also successfully implemented a one-way communication system using the medium of a laser link. The analog signal we input into the audio jack on the transmitter unit was successfully output by the speaker on the receiver unit. This was done by a combination of the PCM encoding/decoding circuitry which enabled the data to be transmitted digitally and also the DPLL cum Training Sequence circuitry which enabled us to successfully reproduce the clock signals, generated on the transmitter unit, at the receiver unit. We used toggle switches to manually switch the transmission between training sequences and real data, and LEDs to help us keep track of what was currently being transmitted. We had also implemented several extra features which aided us in either improving the sound quality of the output or improving the efficiency of implementing our project.

Furthermore, through this experience, we gained valuable practical knowledge on the usage and planning of basic circuit design. We were able to experience first-hand the operational capabilities of the IC chips which we used (e.g. 74HC191 4-bit Synchronous Counter Chip, 74HC297 DPLL Chip, etc.). We learned most importantly that before implementing any chip, we had to be familiar with its datasheet which means understanding chip’s block diagram and also the exact purpose of each pin in the chip.

We also learnt from this experience that the most harrowing part involving design and implementation of electrical systems is the debugging process. As we faced time and manpower constraints, we split the project up into the 5 sub-groups, and each member of the group built their designs individually to maximize time management. The initial debugging of the individual components to ensure that they each performed their specific purposes was rather easy. However, when we began to integrate the different components together, many new problems started to present themselves and we spent much, if not most, of our time trying to debug these problems. However, it was heartening to see that even though we had built the individual components separately, our group displayed a high level of synergy and we were able to solve the problems as a single cohesive unit rather than as separate members.

That said, one point we reflected upon is that though the system worked well, we could have improved it if we were to adopt a ‘parallel’ instead of a ‘serial’ system for our Training Sequence circuits. This means that instead of sending training sequences until frame synchronization is achieved before manually switching to data transmission, we send alternating transmissions of, for example, 128 Training Sequences every 8000 Frames so that the synchronization of the FSYN signals will be refreshed every second. This will ensure that even if the laser link was intercepted, we would not have to redo our clock signal synchronization to continue sending data.

In all, we are glad that we were able to achieve our project requirements as a team. We had managed to put all that we had learnt into practice and achieve the desired outcome of a laser communication system for voice transmission.

5 References

AY 2011/12 Semester 2. EE1003 Lab sheet for Lab 2. Uploaded by Dr. Zhang Jianwen. Retrieved 2012, April 11 from IVLE Workbin.

AY 2011/12 Semester 2. EE1003 74HC165 Datasheet. Uploaded by Dr. Zhang Jianwen. Retrieved 2012, April 11 from IVLE Workbin.

AY 2011/12 Semester 2. EE1003 LM386 Datasheet. Uploaded by Dr. Zhang Jianwen. Retrieved 2012, April 11 from IVLE Workbin.